In order to meet the demand for miniaturization, lightweightedness, high capacity, and versatility in electronic devices, electronic circuit devices should perform more functions in less space. Therefore, various semiconductor chips employed in such electronic devices are required to be thinned and microcircuited, and the technology for packaging such semiconductor chips is also required to be miniaturized and to be made multifunctional. Accordingly, package technology has been actively developed in the direction of realizing the same or different types of semiconductor chips as a single unit package.
For example, in order to improve capacity and processing speed for data of a chip scale package (CSP) and a semiconductor device in which a size of the semiconductor package is only about 110% to 120% of a size of the semiconductor chip, stacked semiconductor packages (SSP) in which a plurality of semiconductor chips are stacked in a vertical direction are being developed. Such a high level of the integration of packaging technology enables more sophisticated electronics to be used without increasing volume.
Meanwhile, in the contemporary stacked semiconductor package, the stacked semiconductor chips are connected to the connection pads of the substrate via the conductive wires. However, an ever-greater number of I/O (input/output) terminals is required, as electronic devices become more multifunctional and highly integrated. Further, as the number of I/O terminals increases, the wire bonding apparatus also increases. Therefore, there is a limit in that a large portion of the semiconductor chip may not be used in the circuit. Particularly, in the case of stacking heterogeneous semiconductor chips, there is a need for a smaller and denser packaging method in order to obtain as much die space as possible.